Principal Engineer - HBM SOC Design and Integration
Location: Richardson
Posted on: June 23, 2025
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Job Description:
Micron Technology is a world leader in innovating memory and
storage solutions that accelerate the transformation of information
into intelligence, inspiring the world to learn, communicate and
advance faster than ever. Our Opportunity Summary: Welcome! The
Heterogeneous Integration Group (HIG) is a division within the
Technology and Products Group (TPG) We are dedicated to developing
and optimizing High Bandwidth Memory (HBM) solutions for AI and ML
applications. Our ultimate goal is to deliver the lowest power per
bit solutions in the industry. Position Overview: As a Principal
HBM SOC Design and Integration Engineer, you will design and
develop next-generation HBM DRAM products. You will collaborate
with domain experts and partners to ensure the success of our HBM
roadmap. Your deep understanding of SOC Architecture, RTL Logic
Design, IP Integration, high-speed interface design,
high-performance computing architectures, and 2.5D & 3D package
integration will help you identify bottlenecks and propose
innovative architectures. Responsibilities: • Analyze customer
requirements and specification documents. Work with IP vendors to
select off-the-shelf IPs, and modify or custom design new ones if
needed. • Review architectural specifications and provide
constructive feedback to help create high-quality specifications. •
Implement project results, whether writing specifications,
developing RTL, integrating IP, testing code, debugging failures.
Run static checks and resolve issues identified by static checks. •
Identify and flag quality issues, performance problems, and
opportunities to reduce power consumption in architecture,
microarchitecture, RTL, or circuits. • Collaborate with the
verification team by reviewing test plans, assisting with writing
assertions and coverage monitors. Offer feedback and suggestions
for test changes. • Debug and identify root causes and solutions
for pre-silicon and post-silicon issues encountered in current HBM
products and architectures. • Engage with customers to support
issues with current HBM architectures and find opportunities to
innovate on future HBM solutions. Minimum Qualifications: • Proven
experience of at least 7 years in microarchitecture and
high-quality RTL development, including writing and testing code in
System Verilog. • Demonstrated 5 years of experience with SOC
integration methods, including DFT/MBIST, CDC, static LP checks,
and SOC interconnects, etc. • Demonstrated ability automating IP
integration using standards such as IP-XACT and tools like
Coretools and Defacto, and writing assertions using SVA. • Proven
expertise in design optimization for performance and low power
consumption, including UPF, static timing analysis, synthesis
design constraints, and closing timing with logic techniques. •
Demonstrated track record of innovation and problem-solving in
high-performance and/or low power SOC development, with experience
delivering highly technical solutions. Preferred Qualifications: •
MSEE or higher in Electrical Engineering or a related field. • 5
years of experience with DRAM operation and JEDEC specifications,
preferably with the HBM product family, and familiarity with
scripting languages such as Python. • 3 years of experience working
on IPs such as UCIE, Memory Controller, NOCs, and using NOC
generation tools. • Proven expertise in some of these areas: memory
array architectures, high-speed signaling, physical layer and
interface development, power delivery and efficiency optimization,
CMOS requirements, packaging, and thermal modeling. • Effective
communication abilities and ability to build relationships, with a
dedication to guiding and nurturing talent. The ability to
efficiently synthesize and convey sophisticated technical concepts
to partners and leadership. A self-motivated, innovative approach
to improving processes or products!
Keywords: , Keller , Principal Engineer - HBM SOC Design and Integration, Engineering , Richardson, Texas
